1. Field of the Invention
The present invention relates to a method and apparatus of fabricating a display device, and more particularly to a method and apparatus of fabricating a display device that is adaptive for minimizing power loss.
2. Description of the Related Art
Generally, a liquid crystal display device controls the light transmissivity of liquid crystal by using an electric field, thereby displaying a picture. For this, the liquid crystal display device includes a liquid crystal display panel where liquid crystal cells are arranged in a matrix, and a driving circuit to drive the liquid crystal display panel. The liquid crystal display panel includes pixel electrodes and a common electrode to apply the electric field to each of the liquid crystal cells. Generally, the pixel electrode is formed on a lower substrate by liquid crystal cells, but the common electrode is formed to be integrated with the entire surface of an upper substrate. Each of the pixel electrodes is connected to a thin film transistor TFT which is used as a switching device. The pixel electrode along with the common electrode drives the liquid crystal cell in accordance with data signals supplied through the thin film transistor.
The lower substrate of the liquid crystal display requires a plurality of mask processes as well as a semiconductor process, thus its fabrication process is complicated and becomes one of the major causes of increase in the manufacturing cost of the liquid crystal display panel. Thus, reducing the number of mask processes in fabricating the lower substrate has become the subject of recent interest. Specifically, as one of the mask processes includes several (in fact, 5) processes such as a deposition process, a cleaning process, photolithography, an etching process, an exfoliation process and an inspection process, reducing the 5-mask process to a 4-mask process has become of interest.
FIGS. 1 and 2 are a plan view and a sectional diagram representing a lower substrate formed in a 4-mask process.
Referring to FIGS. 1 and 2, a lower substrate 1 of a liquid crystal display device includes a thin film transistor TFT (TP) located at an intersection of a data line 4 and a gate line 2, and a pixel electrode 22 connected to a drain electrode 10 of the TFT (TP)
The TFT (TP) includes a gate electrode connected to the gate line 2, a source electrode 8 connected to the data line 4, and a drain electrode 10 connected to the pixel electrode 22 through a drain contact hole 20. Also, the TFT (TP) further includes semiconductor layers 14, 16 to form a conductive channel between the source electrode 8 and the drain electrode 10 by a gate signal supplied to the gate electrode 6. The TFT (TP) selectively supplies a data signal from the data line 4 to the pixel electrode 22 in response to the gate signal from the gate line 2.
The pixel electrode 22 is formed of a transparent conductive material of which light transmissivity is high, and is located at a cell area which is divided by the data line 4 and the gate line 2. The pixel electrode 22 is formed on a protective layer 18 that is spread on the entire surface of the substrate 1, and is electrically connected to the drain electrode 10 through the drain contact hole 20 that runs through the protective layer 18. The pixel electrode 22 generates a potential difference with a common transparent electrode (not shown) formed on an upper substrate (not shown) by the data signal supplied via the TFT (TP). The potential difference causes liquid crystal to be rotated due to dielectric constant anisotropy. The liquid crystal is located between the lower substrate 1 and the upper substrate (not shown). The rotating liquid crystal in this way transmits the light incident from a light source (not shown) via the pixel electrode 22 to the upper substrate.
The fabricating method of the lower substrate of the liquid crystal display device is described as follows in conjunction with FIG. 3A to 3D.
Referring to FIG. 3A, a gate pattern including the gate electrode (6) and a gate line (2) is formed on the lower substrate 1.
For this, a gate metal layer is deposited by a deposition method such as sputtering. The gate metal layer is formed of aluminum Al or aluminum alloy. The gate metal layer is patterned by photolithography using a first mask and an etching process to form the gate electrode 6 and the gate line 2 on the lower substrate 1.
Referring to FIG. 3B, a data pattern is formed on the lower substrate 1 where a gate pattern has been formed. The data pattern includes a gate insulating film 12, an active layer 14, an ohmic contact layer 16, a source electrode 8, a drain electrode 10 and a data line 4.
For this, the gate insulating film 12, first and second semiconductor layers and a data metal layer are sequentially deposited on the lower substrate 1 by a deposition method such as chemical vapor deposition and sputtering. The gate insulating film 12 is formed of inorganic material such as silicon oxide SiOx or silicon nitride SiNx, the first semiconductor layer is formed of amorphous silicon that is not intentionally doped with impurities, the second semiconductor layer is formed of amorphous silicon that is doped with n-type or p-type impurities, and the data metal layer is formed of molybdenum Mo or molybdenum alloy.
A photo resist pattern is formed on the data metal layer by photolithography using a second mask. In this case, the second mask is a diffractive mask having a diffraction part, and the diffractive mask is used at a channel part of the TFT (TP), thus the photo resist pattern of the channel part is relatively lower in height than a source/drain part.
The data metal layer is patterned by a wet etching process using the photo resist pattern, thereby forming the data pattern including the data line 4, a storage electrode (not shown), the source electrode 8 and the drain electrode 10.
Then, the first and second semiconductor layers are simultaneously patterned by a dry etching process using the same photo resist pattern to form an active layer 14 and an ohmic contact layer 16.
And, after removing the photo resist pattern that is relatively lower in height at the channel part by an ashing process, the data metal layer and ohmic contact layer of the channel part are etched by the dry etching process. Accordingly, the active layer of the channel part is exposed to separate the source electrode from the drain electrode.
Then, the photo resist left on the data metal layer is removed by a stripping process.
Referring to FIG. 3C, a protective film 18 is formed on the gate insulating film 12 where the data pattern has been formed.
For this, an insulating material is deposited on the gate insulating film 12 to form the protective film 18. The protective film 18 is formed of inorganic insulating material such as silicon nitride SiNx and silicon oxide SiOx, or organic insulating material such as acrylic organic compound, benzocyclobutene BCB and perflurocyclobutane PFCB. Subsequently, the protective film 18 is patterned by a photolithography using a third mask and the etching process to form a drain contact hole 20. The drain contact hole 20 runs through the protective film 18 to form the drain electrode 10 exposed.
Referring to FIG. 3D, the pixel electrode 22 is formed on the protective film 18.
For this, a transparent metal layer is formed on the protective film 18 by a deposition method such as sputtering. The transparent metal layer is formed of indium tin oxide ITO, indium zinc oxide IZO and indium tin zinc oxide ITZO. Subsequently, the transparent metal layer is patterned by a photolithography using a fourth mask and the etching process to form the pixel electrode 22. The pixel electrode 22 is connected to the drain electrode 10 through the drain contact hole 20 that runs through the protective film 18.
In the known liquid crystal display pattern, the gate pattern and the contact hole formed on the protective film and the channel layer formed between the source and drain electrodes are patterned by the dry etching process. Such a dry etching process is performed by a dry etching apparatus, as shown in FIG. 4.
FIG. 4 is a diagram representing a known dry etching apparatus.
Referring to FIG. 4, the known dry etching apparatus includes a vacuum chamber 30 forming a closed space 90 therewithin to accommodate and etch an object, a plasma generator to receive voltage and generate a discharge voltage for making plasma in the closed space 90, a gas supplier 50 to provide etching gas into the vacuum chamber 30, and a cooling chamber to cool a conductor.
The vacuum chamber 30 includes a body part 40, and a cover part 32 combined with the body part 40 to form the closed space 90 where etching process is performed.
The body part 40 includes a side wall part 40a forming an outer wall of the vacuum chamber 30, and a bottom part 40b formed to be integrated with the side wall part 40a. A pumping line 44 is installed at part of the bottom part 40b. The pumping line 44 is connected to a pump (not shown) that controls the pressure of the closed space 90. Also, part of an electrode forming the plasma generator is located at the central area of the bottom part 40b. 
The cover part 32 is formed to correspond to the upper end part of the body part 40 and is stuck to the body part 40 to be able to open and shut. It is desirable to have a sealing device so that the cover part 32 can prevent gas leakage from the closed space 90 after being assembled with the body part 40. Also, a chamber hole 56 is formed at the cover part 32 to supply plasma etching gas to the closed space 90.
The plasma generator includes a radio frequency generator 70 to generate AC power of high frequency, an RF match box 80 to supply to the vacuum chamber 30 the power generated from the radio frequency generator 70, a first electrode 34 and a second electrode 42 of plate shape to receive the generated power from the radio frequency generator 70 and generate an electric field for forming the plasma. The power generated from the radio frequency generator 70 is transmitted to the RF match box 80 through a first conductor 70a, and the power transmitted to the RF match box 80 is transmitted to a first electrode 34 through a second conductor 70b. 
The radio frequency generator 70 generates a power with frequency of 13.56 MHz and capacity of 10 KW, so that reactive particles forming the plasma can oscillate in both directions, i.e. towards an anode electrode and a cathode electrode. The power is determined by a HF AC voltage and a HF AC current generated from the radio frequency generator 70.
The RF match box 80 squares the impedance of the inside of the vacuum chamber 30 with the impedance of the radio frequency generator 70, and equally sustains the phase of the HF AC voltage supplied from the radio frequency generator 70 and the phase of the AC voltage supplied to the vacuum chamber 30. That is, if the phase of the AC voltage generated from the radio frequency generator 70 does not match the phase of the AC voltage supplied to the vacuum chamber 30, dry etching does not occur, and the dry etching apparatus and the vacuum chamber 30 may be damaged by a sudden energy burst. In order to reduce these risks, the RF match box 80 is installed between the radio frequency generator 70 and the vacuum chamber 30.
The first electrode 34 has a plate shape and is installed at the cover part 32 and connected to the radio frequency generator 70.
The second electrode 42 has a plate shape and is located at the bottom part 40b to form a space for a glow discharge by keeping a designated gap with the first electrode 34. A supporting stand 46 is installed on the upper surface to hold a TFT lower substrate 48 which is to be etched.
The gas supplier 50 includes a gas supplying tube 52 that leads plasma etching gas to the vacuum chamber 30. The plasma etching gas is generated from a gas generator (not shown) that is installed at the outside of the vacuum chamber 30. A gas guide 54 combined with the gas supplying tube 52 and a chamber hole 56 are used to inject the etching gas supplied through the gas supplying tube 52 into the inside of the vacuum chamber 30.
The gas generator (not shown) has a closed space and generates the etching gas, by chemical reaction in the inside of the gas generator. The gas generator generates chlorine gas Cl2, hydrogen chloride HCl, Sulfur Hexafluoride SF6, Oxygen gas O2 and carbon tetrafluoride CF4in accordance with the object being etching.
The gas supplying tube 52 is a pipe that leads the etching gas generated in the gas generator to the vacuum chamber 30, and should be strongly corrosion resistant as the etching gas is poisonous. Also, the gas supplying tube 52 includes a member that prevents impurities from being added to the etching gas flowing into the inside of the dry etching apparatus.
The gas guide 54 transports the etching gas that flows through the gas supplying tube 52 into the vacuum chamber 30. The gas guide 54 should be resistant to corrosion because it too transmits the poisonous gas. The gas guide 54 additionally should have enough durability so that it can bear the pressure of the vacuum formed in the closed space 90. Also, as the gas guide 54 is combined with the chamber hole 56 for the etching gas to be injected into the chamber, it should have a good resistance to corrosion with regard to the plasma.
The cooling chamber 60 cools a second conductor 70b when supplying power to a first electrode 34 through the second conductor 70b after the power generated from the radio frequency generator 70 is transmitted to the RF match box 80 through a first conductor 70a. In other words, because the resistance of the second conductor 70b increases if a large amount of heat is generated in the second conductor 70b, the cooling chamber 60 cools the second conductor 70b and thereby permits the power to be transmitted with a decreased amount of loss. The cooling chamber 60 has a fan that provides air flow into the cooling chamber 60. The second conductor 70b is cooled by an air-cooling system using the fan.
In order to etch the TFT lower substrate 48 with an etching apparatus having such a configuration, firstly, the TFT lower substrate 48 in which the protective film has been deposited is located at the upper surface of the supporting stand 46, and then the pressure of the inside of the closed space 90 is decreased to 7.7 mtorr to 5.6 mtorr, a suitable pressure for forming plasma in when using the pump. A gas that can etch the TFT lower substrate 48 is then supplied through the gas guide 54.
Subsequently, when applying the AC voltage of 13.56 MHz through the radio frequency generator 70 between the first electrode 34 and the second electrode 42, free electrons inside the closed space 90 are accelerated by the electric field and collide with the etching gas molecules. Accordingly, the etching gas molecules gain energy, and then are divided into ions, electrons, radicals by going through an ionization decomposition process to form a plasma. The radicals diffuse and the ions or the electrons move along the direction of the applied electric field and physically or chemically react with the protective film of the TFT lower substrate 48 corresponding to an area in which a contact hole is to be formed, thereby etching the surface. The chemical reactant generated as an etching result is discharged to the outside along the pumping line 44 by the pump to maintain the pressure of the closed space 90.
After the power generated from the radio frequency generator 70 is transmitted to the RF match box 80 through the first conductor 70a, the cooling chamber 60 is used for removing the heat generated in the second conductor 70b to increase the power transmission when supplying the power to the first electrode 34. However, even with this air cooling, the operating temperature of the second conductor 70b is around 40° C., which is well above the ambient temperature. Accordingly, a large amount of the power transmitted to the first electrode 34 is lost from the voltage drop that takes place due to the increase of resistance of the second conductor 70b because the cooling chamber 60 cannot sufficiently cool the heat generated from the second conductor 70b. 